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| CD54HC194, CD74HC194, CD74HCT194 Data sheet acquired from Harris Semiconductor SCHS164G September 1997 - Revised May 2006 High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register Description The 'HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift left mode, and at the shift right (DSR) serial input for the shift right mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR) pin. Features [ /Title (CD74 HC194, CD74H CT194) /Subject (HighSpeed CMOS Logic 4-Bit * Four Operating Modes - Shift Right, Shift Left, Hold and Reset * Synchronous Parallel or Serial Operation * Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC * Asynchronous Master Reset * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH Ordering Information PART NUMBER CD54HC194F3A CD74HC194E CD74HC194M CD74HC194MT CD74HC194M96 CD74HC194NSR CD74HC194PW CD74HC194PWR TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIP Pinout CD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP, TSSOP) CD74HCT194 (PDIP) TOP VIEW MR 1 DSR 2 D0 3 D1 4 D2 5 D3 6 DSL 7 GND 8 16 VCC 15 Q0 14 Q1 13 Q2 12 Q3 11 CP 10 S1 9 S0 CD74HC194PWT CD74HCT194E NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) 2006, Texas Instruments Incorporated 1 CD54HC194, CD74HC194, CD74HCT194 Functional Diagram D0 D1 D2 D3 DSL DSR S0 S1 MR CP 3 4 5 6 7 2 9 10 1 11 15 14 13 12 Q0 Q1 Q2 Q3 GND = 8 VCC = 16 TRUTH TABLE INPUTS OPERATING MODE Reset (Clear) Hold (Do Nothing) Shift Left CP X X Shift Right Parallel Load MR L H H H H H H S1 X l h h l l h S0 X l l l h h h DSR X X X X l h X DSL X X l h X X X Dn X X X X X X dn Q0 L q0 q1 q1 L H d0 OUTPUT Q1 L q1 q2 q2 q0 q0 d1 Q2 L q2 q3 q3 q1 q1 d2 Q3 L q3 L H q2 q2 d3 H = High Voltage Level, h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition, L = Low Voltage Level, l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition, dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock Transition, X = Don't Care, = Transition from Low to High Level 2 CD54HC194, CD74HC194, CD74HCT194 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA Thermal Information Package Thermal Impedance, JA (see Note 2): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 -0.02 -0.02 High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL -4 -5.2 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 V V V V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS 3 CD54HC194, CD74HC194, CD74HCT194 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 3) VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH 4.5 to 5.5 4.5 to 5.5 4.5 2 2 2 V SYMBOL II ICC VI (V) VCC or GND VCC or GND IO (mA) VCC (V) 6 MIN 25oC TYP MAX 0.1 8 -40oC TO 85oC MIN MAX 1 80 -55oC TO 125oC MIN MAX 1 160 UNITS A A 0 6 - - - - - - - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.02 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 0 5.5 - - 0.1 8 - 1 80 - 1 160 A A A 0 5.5 - - - - - 4.5 to 5.5 - 100 360 - 450 - 490 HCT Input Loading Table INPUT CP MR DSL, DSR, Dn Sn UNIT LOADS 0.6 0.55 0.25 1.10 NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g. 360A max at 25oC. 4 CD54HC194, CD74HC194, CD74HCT194 Prerequisite For Switching Function 25oC PARAMETER HC TYPES Max. Clock Frequency (Figure 1) fMAX 2 4.5 6 MR Pulse Width (Figure 2) tW 2 4.5 6 Clock Pulse Width (Figure 1) tW 2 4.5 6 Set-up Time Data to Clock (Figure 3) tSU 2 4.5 6 Removal Time, MR to Clock (Figure 2) tREM 2 4.5 6 Set-Up Time S1, S0 to Clock (Figure 4) tSU 2 4.5 6 Set-up Time DSL, DSR to Clock (Figure 4) tSU 2 4.5 6 Hold Time S1, S0 to Clock (Figure 4) tH 2 4.5 6 Hold Time Data to Clock (Figure 3) tH 2 4.5 6 HCT TYPES Max. Clock Frequency (Figure 1) MR Pulse Width (Figure 2) Clock Pulse Width (Figure 1) Set-up Time, Data to Clock (Figure 3) Removal Time MR to Clock (Figure 2) fMAX tW tW tSU tREM 4.5 4.5 4.5 4.5 27 16 16 14 22 20 20 18 18 24 24 21 MHz ns ns ns 6 30 35 80 16 14 80 16 14 70 14 12 60 12 10 80 16 14 70 14 12 0 0 0 0 0 0 5 24 28 100 20 17 100 20 17 90 18 15 75 15 13 100 20 17 90 18 15 0 0 0 0 0 0 4 20 23 120 24 20 120 24 20 105 21 19 90 18 15 120 24 20 105 21 18 0 0 0 0 0 0 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) MIN MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS - 4.5 12 - 15 - 18 - ns 5 Prerequisite For Switching Function (Continued) 25oC -40oC TO 85oC -55oC TO 125oC MIN 25 MAX MIN 30 MAX UNITS ns PARAMETER Set-up Time S1, S0 to Clock (Figure 4) Set-up Time DSL, DSR to Clock (Figure 4) Hold Time S1, S0 to Clock (Figure 4) Hold Time Data to Clock (Figure 3) SYMBOL tSU tSU tH tH TEST CONDITIONS VCC (V) 4.5 MIN 20 MAX - - 4.5 14 - 18 - 21 - ns - 4.5 0 - 0 - 0 - ns - 4.5 0 - 0 - 0 - ns Switching Specifications PARAMETER HC TYPES Propagation Delay, Clock to Output (Figure 1) Input tr, tf = 6ns TEST CONDITIONS VCC (V) 25oC TYP MAX -40oC TO 85oC -55oC TO 125oC MAX MAX UNITS SYMBOL tPLH, tPHL CL = 50pF 2 4.5 6 14 60 55 175 35 30 75 15 13 140 28 24 10 - 220 44 37 95 19 16 175 35 30 10 - 265 53 45 110 22 19 210 42 36 10 - ns ns ns ns ns ns ns ns ns ns pF MHz pF Propagation Delay, Clock to Q Output Transition Time (Figure 1) tPLH, tPHL tTLH, tTHL CL = 50pF 5 2 4.5 6 Propagation Delay, MR to Output (Figure 2) tPHL CL = 50pF 2 4.5 6 Input Capacitance Maximum Clock Frequency Power Dissipation Capacitance (Notes 4, 5) HCT TYPES Propagation Delay, Clock to Output (Figure 1) Propagation Delay, Clock to Q Output Transition Times (Figure 1) Propagation Delay, MR to Output (Figure 2) Input Capacitance Maximum Clock Frequency Power Dissipation Capacitance (Notes 4, 5) NOTES: CIN fMAX CPD - 5 5 tPLH, tPHL tPLH, tPHL tTLH, tTHL tPHL CIN fMAX CPD CL = 50pF CL = 50pF CL = 50pF - 4.5 5 4.5 4.5 5 5 15 50 60 37 15 40 10 - 46 19 50 10 - 56 22 60 10 - ns ns ns ns pF MHz pF 3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi + (CL VCC2) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 6 Test Circuits and Waveforms tr INPUT LEVEL CP 10% 90% VS tW tPHL Q VS tTHL 90% VS 10% tTLH tf VS 10% VS GND tPLH CP Q VS MR VS tW VS tREM VS tPHL INPUT LEVEL GND INPUT LEVEL GND FIGURE 1. CLOCK PREREQUISITE TIMES AND PROPAGATION AND OUTPUT TRANSITION TIMES FIGURE 2. MASTER RESET PREREQUISITE TIMES AND PROPAGATION DELAYS VALID INPUT LEVEL DATA tSU CP VS tH VS GND INPUT LEVEL GND CP S OR DS VALID VS tSU tH VS INPUT LEVEL GND INPUT LEVEL GND FIGURE 3. DATA PREREQUISITE TIMES FIGURE 4. PARALLEL LOAD OR SHIFT-LEFT/SHIFT-RIGHT PREREQUISITE TIMES 7 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device 5962-8682601EA CD54HC194F3A CD74HC194E CD74HC194EE4 CD74HC194M CD74HC194M96 CD74HC194M96E4 CD74HC194M96G4 CD74HC194ME4 CD74HC194MG4 CD74HC194MT CD74HC194MTE4 CD74HC194MTG4 CD74HC194NSR CD74HC194NSRE4 CD74HC194NSRG4 CD74HC194PW CD74HC194PWE4 CD74HC194PWG4 CD74HC194PWR CD74HC194PWRE4 CD74HC194PWRG4 CD74HC194PWT CD74HC194PWTE4 CD74HC194PWTG4 CD74HCT194E Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP CDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SO SO SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP PDIP Package Drawing J J N N D D D D D D D D D NS NS NS PW PW PW PW PW PW PW PW PW N Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 1 1 25 25 40 TBD TBD Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Lead/Ball Finish A42 SNPB A42 SNPB CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 40 40 250 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 90 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 250 250 250 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type PDIP Package Drawing N Pins Package Eco Plan (2) Qty (RoHS) 16 25 Pb-Free (RoHS) Lead/Ball Finish MSL Peak Temp (3) CD74HCT194EE4 (1) ACTIVE CU NIPDAU N / A for Pkg Type The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SOIC SO TSSOP D NS PW 16 16 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.0 330.0 16.4 16.4 12.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 12.0 8.0 W Pin1 (mm) Quadrant 16.0 16.0 12.0 Q1 Q1 Q1 CD74HC194M96 CD74HC194NSR CD74HC194PWR 2500 2000 2000 6.5 8.2 7.0 10.3 10.5 5.6 2.1 2.5 1.6 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device CD74HC194M96 CD74HC194NSR CD74HC194PWR Package Type SOIC SO TSSOP Package Drawing D NS PW Pins 16 16 16 SPQ 2500 2000 2000 Length (mm) 333.2 346.0 346.0 Width (mm) 345.9 346.0 346.0 Height (mm) 28.6 33.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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